发明名称 LIQUID CRYSTAL DISPLAY (LCD) DEVICE
摘要 A LCD device includes pixels formed of column data lines and row scanning lines. The pixel includes a display element; a first switching unit that performs sampling on each frame data of an input video signal; a first holding unit that configures an SRAM, and holds sub frame data; a second switching unit that causes the sub frame data held in the first holding unit; and a second holding unit that configures a DRAM, and applies output data to the pixel electrode, a pixel control unit that performs an operation of repeating writing the sub frame data in the first holding unit, turning on the second switching units, and rewriting memory content of the second holding units; and a timing control unit. A delay of a certain period of time is sequentially given to a timing at which the pixel control unit turns on the second switching unit.
申请公布号 US2014320482(A1) 申请公布日期 2014.10.30
申请号 US201414259983 申请日期 2014.04.23
申请人 JVC KENWOOD Corporation 发明人 Kawanaka Hiroyuki;Iwasa Takayuki
分类号 G09G3/36 主分类号 G09G3/36
代理机构 代理人
主权项 1. A liquid crystal display (LCD) device, comprising: a plurality of pixels which are formed at crossing portions at which a plurality of column data lines cross a plurality of row scanning lines, wherein the pixel comprises: a display element in which a space, between a pixel electrode and a common electrode opposite to each other, is filled with a liquid crystal and sealed; a first switching unit that performs sampling for a display on each frame data of an input video signal using a plurality of sub frames having a display period of time shorter than one frame period of time through the column data line; a first holding unit that configures an static dynamic random access memory (SRAM) together with the first switching unit, andholds sub frame data obtained by the sampling performed by the first switching unit; a second switching unit that causes the sub frame data held in the first holding unit to be output; and a second holding unit that configures a dynamic random access memory (DRAM) together with the second switching unit, andapplies output data, in which memory content is rewritten according to the sub frame data which is held in the first holding unit and is input through the second switching unit, to the pixel electrode, a pixel control unit that performs an operation of repeating writing the sub frame data in the first holding unit in units of rows in the plurality of pixels,turning on the second switching units of all the plurality of pixels by a trigger pulse after the sub frame data is written in all the plurality of pixels, andrewriting memory content of the second holding units of the plurality of pixels according to the sub frame data that is held in the first holding unit, in units of sub frames; and a timing control unit that performs control such that a delay of a certain period of time is sequentially given to a timing at which the pixel control unit turns on the second switching unit in units of rows of pixels.
地址 Yokohama-shi JP