| 发明名称 |
TEST COVERAGE OF INTEGRATED CIRCUITS WITH MASKING PATTERN SELECTION |
| 摘要 |
A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference. |
| 申请公布号 |
US2014325298(A1) |
申请公布日期 |
2014.10.30 |
| 申请号 |
US201414328788 |
申请日期 |
2014.07.11 |
| 申请人 |
International Business Machines Corporation |
发明人 |
Douskey Steven M.;Fitch Ryan A.;Hamilton Michael J.;Kaufer Amanda R. |
| 分类号 |
G01R31/3177 |
主分类号 |
G01R31/3177 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method of locating faulty logic on a semiconductor chip comprising:
determining failure rates for the semiconductor chip, wherein the semiconductor chip contains one or more logic elements; determining a masking pattern using failure rates, wherein the masking pattern masks less than all of the logic elements using a determination method; and applying a test vector to a selected logic element, wherein a result from a test vector is compared to a reference. |
| 地址 |
Armonk NY US |
