Methods And Systems For Gate Dimension Control In Multi-Gate Structures For Semiconductor Devices

摘要

Methods and systems are disclosed for gate dimension control in multi-gate structures for integrated circuit devices. Processing steps for formation of one or more subsequent gate structures are adjusted based upon dimensions determined for one or more previously formed gate structures. In this way, one or more features of the resulting multi-gate structures can be controlled with greater accuracy, and variations between a plurality of multi-gate structures can be reduced. Example multi-gate features and/or dimensions that can be controlled include overall gate length, overlap of gate structures, and/or any other desired features and/or dimensions of the multi-gate structures. Example multi-gate structures include multi-gate NVM (non-volatile memory) cells for NVM systems, such as for example, split-gate NVM cells having select gates (SGs) and control gates (CGs).

主权项

1. An integrated circuit device having a plurality of multi-gate structures, comprising:
a plurality of first gates for a plurality of multi-gate structures for an integrated circuit device; and a plurality of second gates for the plurality of multi-gate structures; wherein the plurality of multi-gate structures comprise at least one hundred or more multi-gate structures; and wherein overall gate lengths for the plurality of multi-gate structures vary by 10 percent or less.