Creating An Embedded ReRam Memory From A High-K Metal Gate Transistor Structure

摘要

An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

主权项

1. An memory cell comprising:
a transistor element;
wherein the transistor element comprises a first dielectric layer, a second dielectric layer, and a first metal layer,wherein the second dielectric layer is disposed between the first dielectric layer and the first metal layer, andwherein the second dielectric layer comprises a metal oxide, a resistive random access memory (ReRAM) element,
wherein the ReRAM element comprises a third dielectric layer and a second metal layer, andwherein the third dielectric layer comprises the metal oxide; and an electrode interconnecting the transistor element and the ReRAM element,
wherein the first dielectric layer directly contacts a first portion of the electrode,wherein the third dielectric layer directly contacts a second portion the electrode.