| 发明名称 |
Method and apparatus for coordinating memory operations among diversely-located memory components |
| 摘要 |
A specific address and control bus, and a data bus (108), are connected to a memory controller (102) and a memory module (103). The data bus using differential signaling, has symbol time lesser than specific address and control bus symbol time. |
| 申请公布号 |
EP2273376(B1) |
申请公布日期 |
2014.10.29 |
| 申请号 |
EP20100179110 |
申请日期 |
2002.04.23 |
| 申请人 |
RAMBUS INC. |
发明人 |
WARE, FREDERICK;TSERN,, ELY K.;PEREGO, RICHARD E.;HAMPEL, CRAIG E. |
| 分类号 |
G06F12/00;G06F13/16;G06F13/40;G06F13/42;G11C8/00;G11C11/401;G11C29/00;G11C29/02 |
主分类号 |
G06F12/00 |
| 代理机构 |
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代理人 |
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