| 摘要 |
Trellis decoder and decoding method for Viterbi or Log-MAP decoding comprising a radix four, eight or sixteen add-compare-select (ACS) circuit including at least two ACS layer modules (302, 304) coupled in series for iteratively generating new state metrics (q(t+1), q(t+2)) from old state metrics (q(t)) and branch metrics (x(t), x(t+1)), the ACS circuit further including a feedback register (306) for storing state metrics, wherein the ACS layer modules are configured to operate according to carry-save arithmetic, the feedback register (306) is configured to store carry components of the state metrics, and wherein plurality of multiplexers are configured to perform a selection of a maximum state metric in carry-save arithmetic. |
