发明名称 Precise exception signaling for multiple data architecture
摘要 <p>Methods and systems of the present invention provide a non-signaling exception mode, in which a processor does not signal that an exception has occurred and, instead, indicates an exception in the output register only for the specific operations that caused the exception while allowing operation on the other elements to proceed and the result to be written to the output register. In particular the method provides an input vector 202,206 comprising a plurality of elements is received by a processor. The processor determines if performing a first operation on a first element will cause an exception and if so, writes an indication of the exception 208c caused by the first operation to a first portion of an output vector 208 stored in an output register. A second operation can be performed on a second element with the result of the second operation being written to a second portion 208d of the output vector stored in the output register.</p>
申请公布号 GB2513448(A) 申请公布日期 2014.10.29
申请号 GB20140003028 申请日期 2014.02.20
申请人 MIPS TECHNOLOGIES, INC. 发明人 LLIE GARBACEA;JAMES ROBINSON
分类号 G06F9/30 主分类号 G06F9/30
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