发明名称 マルチダイメモリ素子
摘要 An integrated circuit (IC) package includes an interface die and a separate storage die. The interface die has a synchronous interface to receive memory access commands from an external memory controller, and has a plurality of clockless memory control interfaces to output row and column control signals that correspond to the memory access commands. The storage die has a plurality of independently accessible storage arrays and corresponding access-control interfaces to receive the row and column control signals from the clockless memory control interfaces, each of the access-control interfaces including data output circuitry to output read data corresponding to a given one of the memory access commands in a time-multiplexed transmission.
申请公布号 JP5616636(B2) 申请公布日期 2014.10.29
申请号 JP20090541577 申请日期 2007.12.13
申请人 ラムバス・インコーポレーテッド 发明人 ベスト,スコット;リ,ミン
分类号 G11C7/00;G06F12/00;G11C5/00;G11C11/401 主分类号 G11C7/00
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