发明名称 Methods of forming trench/hole type features in a layer of material of an integrated circuit product
摘要 One illustrative method disclosed herein involves forming a layer of insulating material, forming a patterned layer of photoresist above the layer of insulating material, wherein the patterned layer of photoresist has an opening defined therein, forming an internal spacer within the opening in the patterned layer of photoresist, wherein the spacer defines a reduced-size opening, performing an etching process through the reduced-size opening on the layer of insulating material to define a trench/hole type feature in the layer of insulating material, and forming a conductive structure in the trench/hole type feature in the layer of insulating material.
申请公布号 US8871649(B2) 申请公布日期 2014.10.28
申请号 US201313834946 申请日期 2013.03.15
申请人 GLOBALFOUNDRIES Inc.;Renesas Electronics Corporation;International Business Machines Corporation 发明人 Jang Linus;Matsui Yoshinori;Tseng Chiahsun
分类号 H01L21/311;H01L21/768 主分类号 H01L21/311
代理机构 Amerson Law Firm, PLLC 代理人 Amerson Law Firm, PLLC
主权项 1. A method of fabricating a reduced-sized opening on a layer of an insulating material, the method comprising: forming a layer of insulating material; forming a patterned layer of photoresist above said layer of insulating material, said patterned layer of photoresist having an opening defined therein, wherein forming said patterned layer of photoresist comprises developing said layer of photoresist with a positive tone developer; forming an internal spacer within said opening in said patterned layer of photoresist, wherein said internal spacer defines a reduced-size opening; performing an etching process through said reduced-size opening on said layer of insulating material to define a trench/hole type feature in said layer of insulating material; and forming a conductive structure in said trench/hole type feature in said layer of insulating material.
地址 Grand Cayman KY