发明名称 |
Low cost adjacent double error correcting code |
摘要 |
A device includes a controller configured to provide a data word and check bits for the data word to decoding logic, the decoding logic configured to generate a decoding of the data word and check bits for the data word in conformance with an H-matrix having the following properties:;(a) no all 0 columns;;(b) all columns are distinct;;(c) no linear dependency involving three or less columns;;(d) no linear dependency involving columns Ci, Cj, Ck, Cm, where m>k>j>i, where j=i+1 and m=k+1; and;(e) no linear dependency involving columns Ci, Cj, Ck, Cm, where m>k>j>i, where (j=i+1 and m−k=q) or (k=j+1 and m−i=q) or (m=k+1 and j−i=q) for all integer values of q such that q>1 and q<=d, where d>=2 and d<=n−1 where n−k is a number of the check bits. |
申请公布号 |
US8875002(B1) |
申请公布日期 |
2014.10.28 |
申请号 |
US201213535541 |
申请日期 |
2012.06.28 |
申请人 |
Cypress Semiconductor Corporation |
发明人 |
Dutta Avijit |
分类号 |
H03M13/13;G06F11/08;H03M13/11;G06F11/10 |
主分类号 |
H03M13/13 |
代理机构 |
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代理人 |
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主权项 |
1. A device, comprising:
a controller configured to provide a data word and check bits for the data word to decoding logic; the decoding logic configured to generate a decoding of the data word and check bits for the data word in conformance with an H-matrix having the following properties: (a) no all 0 columns; (b) all columns are distinct; (c) no linear dependency involving three or less columns; (d) no linear dependency involving columns Ci, Cj, Ck, Cm, where m>k>j>i, where j=i+1 and m=k+1; and (e) no linear dependency involving columns Ci, Cj, Ck, Cm, where m>k>j>i, where (j=i+1 and m−k=q) or (k=j+1 and m−i=q) or (m=k+1 and j−i=q) for all integer values of q such that q>1 and q<=d, where d>=2 and d<=n−1 where n−k is a number of the check bits. |
地址 |
San Jose CA US |