发明名称 Volatile memory elements with soft error upset immunity
摘要 Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.
申请公布号 US8873278(B1) 申请公布日期 2014.10.28
申请号 US201313732737 申请日期 2013.01.02
申请人 Altera Corporation 发明人 Xu Yanzhong;Watt Jeffrey T.
分类号 G11C11/00 主分类号 G11C11/00
代理机构 Treyz Law Group 代理人 Treyz Law Group ;Tsai Jason
主权项 1. Memory element circuitry, comprising: a memory element having at least four interconnected inverter-type transistor pairs and at least one access circuit, wherein the memory element is configured to store data on internal nodes; and circuitry that loads data into the memory element while changing a magnitude of a power supply voltage that powers the memory element.
地址 San Jose CA US