Hierarchical buffer system enabling precise data delivery through an asynchronous boundary

摘要

The present invention provides a system and method for controlling data entries in a hierarchical buffer system. The system includes an integrated circuit device with a memory core, a high speed upstream data bus, and a plurality of 1st tier buffers that receive data from the memory. The system further includes a 2nd tier transfer buffer spanning a plurality of asynchronous timing domains that delivers the data onto the upstream data bus to minimize gaps in a data transfer. The method includes managing the buffers to allow data to flow from a plurality of 1st tier buffers through a 2nd tier transfer buffer, and delivering the data onto a high speed data bus with pre-determined timing in a manner which minimizes latency to the extent that the returning read data beats are always transmitted contiguously with no intervening gaps.

主权项

1. A method of controlling data entries in a hierarchical buffer system for a plurality of memory sources, the method comprising:
managing buffers to move multiple data packets from a plurality of 1st tier hardware buffers into a 2nd tier hardware transfer buffer; calculating precise delivery times for the multiple data packets in the 2nd tier hardware transfer buffer to minimize gap in a data transfer; enabling the 2nd tier hardware transfer buffer to serve as an asynchronous boundary to permit data to cross a plurality of clock domains running at different frequencies; and delivering the data in the 2nd tier hardware transfer buffer onto an upstream data bus, and wherein said multiple data packets are delivered at the calculated precise delivery times.