| 发明名称 | Semiconductor package and method of manufacturing the same | ||
| 摘要 | Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings. | ||
| 申请公布号 | US8871569(B2) | 申请公布日期 | 2014.10.28 |
| 申请号 | US201314081697 | 申请日期 | 2013.11.15 |
| 申请人 | Samsung Electro-Mechanics Co., Ltd. | 发明人 | Lee Doo Hwan;Jeong Tae Sung;Chung Yul Kyo |
| 分类号 | H01L21/00;H01L23/00;H01L21/52;H01L21/54;H01L23/31;H01L21/56;H01L21/768;H01L23/538;H01L21/78 | 主分类号 | H01L21/00 |
| 代理机构 | Ladas & Parry, LLP | 代理人 | Ladas & Parry, LLP |
| 主权项 | 1. A method of manufacturing a semiconductor package, the method comprising: preparing a mold having cavity forming patterns formed thereon; forming a molding member on the mold; removing the mold from the molding member to thereby form cavities in the molding member; mounting devices in the cavities of the molding member; forming an insulating member on the molding member and the devices; forming a circuit layer on the insulating member, the circuit layer including vias and connection pads; forming a solder resist layer on the circuit layer, the solder resist layer having openings exposing upper portions of the connection pads; and forming solder balls in the openings. | ||
| 地址 | Gyunggi-Do KR | ||