发明名称 |
Information processing apparatus, information processing system, controlling method for information processing apparatus and program |
摘要 |
An information processing apparatus includes a first parity production section for producing a first error detection code for detecting an error of data. A second parity production section produces a second error detection code for detecting an error of the data from the first error detection code. A first parity checking section detects an error of the retained data as a first error using the retained first error detection code. A second parity checking section detects an error of the retained data as a second error using the retained second error detection code. A control amount outputting section outputs, when an occurrence rate of a first error is equal to or lower than a first threshold value, a control amount for controlling a power supply voltage or a frequency using a second threshold value as a target value for an occurrence rate of a second error. |
申请公布号 |
US8874978(B2) |
申请公布日期 |
2014.10.28 |
申请号 |
US201213416431 |
申请日期 |
2012.03.09 |
申请人 |
Sony Corporation |
发明人 |
Hirairi Koji |
分类号 |
G06F11/00;G01R31/30;H03M13/00;G06F11/10;G06F1/32;G06F11/07;H04L1/20;G01R31/317;G01R31/3181;H03M13/09 |
主分类号 |
G06F11/00 |
代理机构 |
Rader, Fishman & Grauer PLLC |
代理人 |
Rader, Fishman & Grauer PLLC |
主权项 |
1. An information processing apparatus, comprising:
a first retention section configured to retain and output data in accordance with a clock signal; a processing section configured to process the outputted data and output the data as processed data; a first error detection code production section configured to produce a first error detection code for detecting an error of the processed data from the processed data; a second error detection code production section configured to produce a second error detection code for detecting an error of the processed data from the first error detection code; a second retention section configured to retain the processed data and the first and second error detection codes therein in accordance with the clock signal; a first error detection section configured to detect an error of the retained processed data as a first error using the retained first error detection code; a second error detection section configured to detect an error of the retained processed data as a second error using the retained second error detection code; and a control amount outputting section configured to control, when an occurrence rate of the first error in said first error detection section is equal to or lower than a first threshold value while an occurrence rate of the second error in said second error detection section is higher than a second threshold value, a power supply voltage to said processing section or a frequency of the clock signal using the second threshold value as a target value for the occurrence rate of the second error based on a predetermined relationship between the occurrence rate of the second error and the power supply voltage or the frequency. |
地址 |
Tokyo JP |