Stack package

摘要

A stack package may include a plurality of chips stacked with a plurality of layers; and a chip selection controller configured to provide a reference and chip selection control signal to the plurality of chips. Each chip may comprise: a reference signal controller configured to transmit the reference signal through a first line interconnecting the plurality of chips; a chip selection delay unit configured to control a delay timing point of the chip selection control signal to transmit the control result to each node of a second line interconnecting the plurality of chips; a delay-time-difference sensing unit configured to calculate a delay time difference between a signal applied to each node of the first and second line to generate chip selection information corresponding to the calculated delay time difference; and a memory unit configured to store the chip selection information.

主权项

1. A stack package comprising:
a plurality of stacked chips; and a chip selection controller configured to provide a reference signal and a chip selection control signal to the plurality of chips, wherein each of the chips comprise:
a reference signal controller configured to transmit the reference signal through a first line interconnecting the plurality of chips;a chip selection delay unit configured to control a delay timing point of the chip selection control signal in different ways so as to transmit the control result to each node of a second line interconnecting the plurality of chips;a delay-time-difference sensing unit configured to calculate a delay time difference between a signal applied to each node of the first line and a signal applied to each node of the second line so as to generate chip selection information corresponding to the calculated delay time difference; anda memory unit configured to store the chip selection information.