Image encoder and image processing system

摘要

According to one embodiment, an image encoder configured to write coded image data in a memory includes an encoding module, a write address determining module, and a memory controller. The encoding module divides original image data including a plurality of pixels into a plurality of block lines, divides each block line into a plurality of sub-block lines, encodes the original image data in each sub-block line, and generates a plurality of coded sub-block lines. The write address determining module determines a write address of the memory in each coded sub-block line based on a number of the sub-block lines, an original image data size of the original image data, and image coding rate. The memory controller writes the coded sub-block line in the write address corresponding to the coded sub-block line.

主权项

1. An image encoder configured to write coded image data in a memory, the encoder comprising:
an encoding module configured to divide original image data comprising a plurality of pixels into a plurality of block lines, to divide each block line into a plurality of sub-block lines, to encode the original image data in each sub-block line, and to generate a plurality of coded sub-block lines; a write address determining module configured to determine a write address of the memory in each coded sub-block line based on a number of the sub-block lines, an original image data size of the original image data, and image coding rate; and a memory controller configured to write the coded sub-block line in the write address corresponding to the coded sub-block line, wherein: the coded sub-block line comprises a first coded sub-block line comprising a starting pixel of the block line and a second coded sub-block line subsequent to the first coded sub-block line, and the memory controller:
determines a head address and an end address which define a storage area in the memory, the first and second coded sub-block lines being able to be stored in the storage area;determines the head address as a first write address;determines an address returning from the end address by a write unit of the memory as a second write address;writes the first coded sub-block line in a reverse direction of a vertical direction of a memory space in a first write area where the first write address is a starting point; andwrites the second coded sub-block line in a second write area where the second write address is a starting point.