发明名称 Systems and methods for test time outlier detection and correction in integrated circuit testing
摘要 Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
申请公布号 US8872538(B2) 申请公布日期 2014.10.28
申请号 US201313803268 申请日期 2013.03.14
申请人 Optimal Plus Ltd. 发明人 Balog Gil;Linde Reed;Golan Avi
分类号 G01R31/26;G01R31/317;G01R31/28;G01R31/3185 主分类号 G01R31/26
代理机构 Occhiuti & Rohlicek LLP 代理人 Occhiuti & Rohlicek LLP
主权项 1. A method of semiconductor testing comprising: while a test program is being applied to a semiconductor device, deciding that said device is testing too slowly and that based on a yield criterion said device is to be prevented from completing said test program; and preventing said device from completing said test program; wherein after said device has been prevented from completing said test program and if there is at least one remaining untested semiconductor device, said test program is applied to at least one of said remaining untested semiconductor devices.
地址 Nes-zionna IL