Trace routing within a semiconductor package substrate

摘要

A semiconductor device includes a substrate configured with a plurality of conductive traces. The traces are configured to electrically couple to an integrated circuit (IC) die and at least one of the plurality of conductive traces includes first electrically conductive portions in a first electrically conductive layer of the substrate, second electrically conductive portions in a second electrically conductive layer of the substrate, and first electrically conductive connections between the first electrically conductive portions and the second electrically conductive portions. The first and second electrically conductive portions and the first electrically conductive connections form a continuous path along at least a portion of the at least one of the conductive traces. Time delay of conducting a signal along the at least one of the conductive traces is within a specified amount of time of time delay of conducting a signal along another one of the plurality of conductive traces.

主权项

1. A semiconductor device comprising:
a substrate; an integrated circuit (IC) die coupled to the substrate; and a plurality of metal traces in the substrate, wherein at least one of the metal traces includes
a plurality of first metal portions in a first metal layer,a plurality of second metal portions in a second metal layer,a plurality of first vias connecting the first metal portions to the second metal portions so that the at least one metal trace is continuous along a length of the at least one metal trace, and the first metal portions, the second metal portions, and the first vias are positioned in a single vertical plane with respect to a top major surface and a bottom major surface of the substrate, wherein the routing delay of the at least one metal trace matches routing delay of another one of the plurality of metal traces within a specified tolerance.