| 发明名称 |
Data forwarding circuits and methods for memory devices with write latency |
| 摘要 |
A memory device can include a memory array section; a write first-in-first-out circuit (FIFO) configured to transfer write data to the memory array portion; at least one store circuit configured to store a copy of at least a portion of the write data stored in the write FIFO; and an address compare section configured to store write addresses corresponding to the write data of the forwarding circuit. |
| 申请公布号 |
US8873264(B1) |
申请公布日期 |
2014.10.28 |
| 申请号 |
US201313795134 |
申请日期 |
2013.03.12 |
| 申请人 |
Cypress Semiconductor Corporation |
发明人 |
Tran Thinh;Tzou Joseph |
| 分类号 |
G11C15/00;G11C7/22 |
主分类号 |
G11C15/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory device, comprising:
a memory array section; a write first-in-first-out circuit (FIFO) configured to transfer write data to the memory array section; at least one store circuit configured to store a copy of at least a portion of the write data stored in the write FIFO; and an address compare section configured to store write addresses, from any of a plurality of different ports, corresponding to the copy of the write data in the store circuit. |
| 地址 |
San Jose CA US |
