| 摘要 |
PROBLEM TO BE SOLVED: To provide a receiving circuit capable of reducing a determination error rate.SOLUTION: A receiving circuit includes: a sampling circuit (102) for sampling boundary data synchronously with a first clock signal and sampling center data synchronously with a second clock signal from an input data signal; a determination feedback equalization circuit (103) for determining equalization and binarization of the center data sampled by the sampling circuit by using an equalization coefficient (103); a phase difference operation circuit (109) for calculating a phase difference of output data of the determination feedback equalization circuit on the basis of the equalization coefficient of the determination feedback equalization circuit; a first phase adjustment circuit (111) for adjusting a phase of the first clock signal on the basis of phase information detected by a phase detection circuit; and a second phase adjustment circuit (112) for adjusting a phase of the second clock signal on the basis of the phase information detected by the phase detection circuit and the phase difference calculated by the phase difference operation circuit. |
