发明名称 LATCH CIRCUIT, SCAN TEST OBJECT CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD FOR LATCH CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To enable a latch circuit to operate in any of different scan systems.SOLUTION: A data latch part 20 of a latch circuit 16 forming a scan chain stores data Si and Di, and outputs the stored data. A latch control part 22 includes: an input terminal to which a first operation signal corresponding to a first scan system is input; and an input terminal to which a second operation signal corresponding to a second scan system is input. The latch control part outputs a first control signal for allowing the data latch part to operate in the first scan system to the data latch part according as the first operation signal is input, and outputs a second control signal for allowing the data latch part to operate in a second scan system to the data latch part according as the second operation signal is input. Thus, it is possible to allow the latch circuit to operate in any of the first scan system and the second scan system.</p>
申请公布号 JP2014202532(A) 申请公布日期 2014.10.27
申请号 JP20130077055 申请日期 2013.04.02
申请人 FUJITSU LTD 发明人 SUGIYAMA ITSUMI
分类号 G01R31/28;H01L21/822;H01L27/04 主分类号 G01R31/28
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