WAFER LEVEL ARRAY OF CHIPS AND METHOD THEREOF

摘要

A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.

主权项

1. A method of wafer level chip package, comprising:
providing a semiconductor wafer having at least two adjacent chips and a carrier layer covering the chips, each chip having at least one device and at least one extending-line disposed in at least one extending-line protection area in the semiconductor wafer; litho-etching a backside of the semiconductor wafer to form at least two recesses between the chips; and overall etching the backside of the semiconductor wafer to expand the recesses such that the recesses merging as an inter-chip trench, and exposing the extending-line protection area to form at least one extending-line protection.