发明名称 |
RECONFIGURABLE LOAD-REDUCED MEMORY BUFFER |
摘要 |
A memory module can include a data buffer having a data bus interface and a dynamic random access memory (DRAM) coupled to the data buffer. The memory module may also include a switch connected in parallel with the data buffer, wherein the switch can selectively bypass the data buffer. In one example, the memory module also includes a registered buffer having an address bus interface, where the switch may selectively bypass the data buffer based on a program signal obtained from an address bus via the address bus interface. |
申请公布号 |
US2014313838(A1) |
申请公布日期 |
2014.10.23 |
申请号 |
US201414173221 |
申请日期 |
2014.02.05 |
申请人 |
Chiu Scott;Arafa Mohamed |
发明人 |
Chiu Scott;Arafa Mohamed |
分类号 |
G11C7/10 |
主分类号 |
G11C7/10 |
代理机构 |
|
代理人 |
|
主权项 |
1. A memory module comprising:
a data buffer having a data bus interface; a dynamic random access memory coupled to the data buffer; and a switch connected in parallel with the data buffer, the switch to selectively bypass the data buffer when the data buffer is powered down and the memory module is being addressed. |
地址 |
Folsom CA US |