PHASE-LOCKED LOOP DEVICE WITH MANAGED TRANSITION TO RANDOM NOISE OPERATION MODE

摘要

A phase-locked loop device is configured to manage a transition from a relaxation-oscillation mode to a random noise operation mode. It is designed for progressively reducing proportional and integral coefficients that are implemented in a loop filter of the PLL device. Recovering the last values formerly used for the proportional and integral coefficients is also provided, in case the PLL lock state is lost. Such transition management may be combined with using a voltage-controlled oscillator within the PLL device, which has several control inputs.

主权项

1. A phase-locked loop (PLL) device with managed transition to random noise operation mode, comprising:
a bang-bang non-linear phase comparator comprising
a first comparator input configured to receive a reference signal having a reference frequency,a second comparator input configured to receive a frequency-converted signal, and a comparator output configured to produce an error signal having one of two discrete values; a loop filter of proportional-integral type, comprising
a filter input connected to the comparator output,at least one configuration input configured to receive respective values of a proportional coefficient and an integral coefficient,the loop filter configured to produce at a filter output a time-filtered error signal in accordance with the values received for the proportional and integral coefficients; a voltage-controlled oscillator (VCO) module, comprising
at least one control input configured to receive a control signal, anda VCO output to produce a VCO signal having a VCO frequency varying as a function of the control signal; at least one control connection configured to connect the filter output to the control input of the VCO module, whereby the control signal is based on the time-filtered error signal; a frequency converter, connected at an input to the VCO output, and configured to produce at a converter output the frequency-converted signal based on the VCO signal, the converter output being connected to the second comparator input; and a lock detector configured to produce
a lock signal indicating whether a lock condition is met during a current operation of the PLL device, andan oscillation-length value indicating a duration between two successive sign reversals for a phase time-shift currently existing for the frequency-converted signal relative to the reference signal; wherein the PLL device further comprises a loop controller connected at an input to receive the lock signal and the oscillation-length value, and connected at an output to the at least one configuration input of the loop filter, and configured to select and produce at the output the values of the proportional and integral coefficients based on the following tests which are continually executed during the operation of the PLL device:
test i: if the lock condition is met, then replacing the respective values of the proportional and integral coefficients as currently used within the loop filter with new values selected respectively for the proportional and integral coefficients, each of the new values being smaller than the corresponding values currently used; andtest ii: if the lock condition is not met and the duration between two successive sign reversals for the phase time-shift is longer than a first duration threshold, then replacing the respective values of the proportional and integral coefficients as currently used within the loop filter (2) with former values which were used respectively for the proportional and integral coefficients before the values currently used had been selected.