SYSTEM AND METHOD FOR STATIONARY FINITE IMPULSE RESPONSE FILTERS IN PROGRAMMABLE MICROELECTRONIC CIRCUITS

摘要

A Field Programmable Gate Array (FPGA) to implement channel equalization to mitigate group velocity dispersion in an optical system. In one embodiment, a mapping is loaded into the FPGA whereby the in-phase and quadrature components of the baseband sequence to be filtered are routed to accumulators to form various sums, where each sum is multiplied by a corresponding distinct filter tap coefficient value according to the mapping to form various products, and where the products are summed to provide the in-phase and quadrature components of the filtered output.

主权项

1. An apparatus to filter a first input sequence to provide a filtered output, the apparatus comprising:
a first memory to store a time window of the first input sequence; and a Field Programmable Gate Array (FPGA) programmed with a mapping to implement a filter, the filter associated with a set of filter tap coefficients, where the set of filter tap coefficients is represented by a set of distinct values, wherein the mapping associates for each distinct value a set of the time window of the first input sequence, the FPGA programmed to implement a process comprising:
summing for each distinct value an associated set of the time window of the first input sequence according to the mapping to provide a first plurality of sums, each sum in the first plurality of sums associated with a distinct value;multiplying each sum in the first plurality of sums with its corresponding distinct value to provide a first plurality of products; andsumming each product in the first plurality of products to provide a portion of the filtered output.