Die Seal Layout for VFTL Dual Damascene in a Semiconductor Device

摘要

A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area allowing the die seal area to he disregarded for purposes of calculating a process window.

主权项

1. A semiconductor device, comprising:
an active area having a plurality of active elements, each of the active elements being defined by a first trench overlapping with a first via, each of the active elements including a first continuous metal filling disposed in the trench and the via; and a die seal defined by a second trench, a second continuous metal filling disposed in the trench.