| 发明名称 |
Methods and Systems for Distributing Clock and Reset Signals |
| 摘要 |
A distribution network, comprises: circuit blocks having counters, wherein the counters are synchronized relative to an input signal; drivers connected in a balanced tree for distributing the input signal synchronously to the circuit blocks; and drivers connected in an unbalanced tree for distributing a reset signal to the circuit blocks, wherein the input signal is distributed via the balanced tree as a function of the reset signal. |
| 申请公布号 |
US2014317434(A1) |
申请公布日期 |
2014.10.23 |
| 申请号 |
US201414170064 |
申请日期 |
2014.01.31 |
| 申请人 |
Kool Chip, Inc. |
发明人 |
Chalasani Prasad;Rao Venkata N.S.N. |
| 分类号 |
G06F1/04;G06F1/10 |
主分类号 |
G06F1/04 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A distribution network, comprising:
circuit blocks having counters, wherein the counters are synchronized relative to an input signal; drivers connected in a balanced tree for distributing the input signal synchronously to the circuit blocks; and drivers connected in an unbalanced tree for distributing a reset signal to the circuit blocks, wherein the input signal is distributed via the balanced tree as a function of the reset signal. |
| 地址 |
San Jose CA US |
