发明名称 WIRING BOARD
摘要 A wiring board includes first insulating layers and second insulating layers formed on a core layer in this order; a third insulating layer and a solder resist layer formed on another surface of the core layer in this order, first wiring layers and second wiring layers formed in the first insulating layers and the second insulating layers, respectively, wherein a first end surface of the first via wiring exposes from the first surface of the outermost first insulating layer to be directly connected with an outermost second wiring layer, the first via wiring and the outermost second wiring layer being separately formed, the first surface of the outermost first insulating layer and the first end surface of the first via wiring are polished surfaces, smooth surfaces and are flush with each other, and the wiring density of the second wiring layers is higher than that of the first wiring layers.
申请公布号 US2014311771(A1) 申请公布日期 2014.10.23
申请号 US201414247355 申请日期 2014.04.08
申请人 SHINKO ELECTRIC INDUSTRIES CO., LTD. 发明人 SHIMIZU Noriyoshi;SAKAGUCHI Hitoshi;KANEDA Wataru;TANAKA Masato;ROKUGAWA Akio
分类号 H05K1/02 主分类号 H05K1/02
代理机构 代理人
主权项 1. A wiring board comprising: a core layer; a plurality of first insulating layers formed on a first surface of the core layer; a plurality of second insulating layers formed on a first surface of an uppermost first insulating layer of the plurality of first insulating layers; a third insulating layer formed on a second surface of the core layer, the second surface being opposite to the first surface of the core layer; a solder resist layer formed on the third insulating layer, a plurality of first wiring layers alternately formed in the plurality of first insulating layers at a first surface side of the core layer; a plurality of first via wirings formed by filling metal in via holes in the plurality of first insulating layers, respectively; a plurality of second wiring layers alternately formed in the plurality of second insulating layers at the first surface of the uppermost first insulating layer; a plurality of second via wirings formed by filling metal in via holes in the plurality of second insulating layers, respectively; and a third wiring layer formed at the third insulating layer; wherein each of the plurality of first insulating layers, and the third insulating layer are composed of a thermosetting insulating resin, respectively, wherein each of the plurality of second insulating layer, and the solder resist layer are composed of a photosensitive resin, respectively, wherein the plurality of second wiring layers are formed on the first surface of the uppermost first insulating layer and a first end surface of the first via wiring that is embedded in the uppermost first insulating layer and the plurality of second wiring layers are connected to the plurality of first wiring layers through the first via wiring, wherein the first end surface of the first via wiring that is embedded in the uppermost first insulating layer exposes from the first surface of the uppermost first insulating layer to be directly connected with a lowermost second wiring layer, the lowermost second wiring layer being formed on the first surface of the uppermost first insulating layer in the plurality of second wiring layers, wherein the first surface of the uppermost first insulating layer and the first end surface of the first via wiring that is embedded in the uppermost first insulating layer are polished surfaces, wherein the first end surface of the first via wiring that is embedded in the uppermost first insulating layer and the first surface of the uppermost first insulating layer are flush with each other, and wherein the wiring density of the plurality of second wiring layers is higher than the wiring density of the plurality of first wiring layers.
地址 Nagano JP