发明名称 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME
摘要 A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surf ace protection film formed to cover the top wiring layer is flattened by CMP.
申请公布号 US2014312493(A1) 申请公布日期 2014.10.23
申请号 US201414320686 申请日期 2014.07.01
申请人 RENESAS ELECTRONICS CORPORATION 发明人 Suzuki Shinya
分类号 H01L23/00;H01L23/485 主分类号 H01L23/00
代理机构 代理人
主权项 1. A semiconductor device comprising: (a) a semiconductor substrate; (b) a semiconductor element formed over the semiconductor substrate; (c) a multilayer wiring layer formed over the semiconductor element; (d) a pad formed in a top layer of the multilayer wiring layer; (e) a surface protection film which is formed over the pad and has an opening which reaches the pad; and (f) a bump electrode which is formed over the surface protection film and electrically coupled with the pad by filling the opening, wherein the bump electrode is larger than the pad so as to have an overlap region which overlaps the pad in a plan view and a non-overlap region which does not overlap the pad in a plan view, wherein over the top layer of the multilayer wiring layer, (g) a first wiring comprised of a power line or signal line in addition to the pad, and (h) a dummy pattern different from the first wiring are formed, and wherein the first wiring formed in the same layer as the pad is formed in a layer under the non-overlap region of the bump electrode.
地址 Kawasaki-shi JP