发明名称 POWERLINE INTERFERENCE INDICATION AND MITIGATION FOR DSL TRANSCEIVERS
摘要 The present disclosure outlines mechanisms, systems, methods, techniques and algorithms that gateway devices and powerline communication (PLC) networks can follow to mitigate adverse effects from the aforementioned inter-network interference. Although the present disclosure provides implementation details for G.hn and VDSL2, the mechanisms, systems, methods, techniques and algorithms described herein are equally applicable to other similar technologies. Therefore, when referring to non-implementation specific systems, methods, techniques and algorithms the term PLC is used to refer to a powerline network and the term customer premises equipment (CPE) is used to refer to a home-gateway device.
申请公布号 EP2793403(A1) 申请公布日期 2014.10.22
申请号 EP20140164690 申请日期 2014.04.15
申请人 METANOIA COMMUNICATIONS INC. 发明人 MUNGALL, SAM;MANTRI, RAVI
分类号 H04B3/32;H04J3/02;H04J3/14;H04J3/16;H04L12/24;H04M11/06 主分类号 H04B3/32
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