| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To shorten the testing time. <P>SOLUTION: A source line voltage control circuit 31 controls a source line SL0 in a test mode to a potential (second voltage) different from a potential (first voltage) in a read operation of a normal mode in response to a test mode signal TM supplied from a test mode control circuit. When the potential of the source line SL0 is controlled to the first voltage, a cell current corresponding to an erasing state or a writing state flows into a memory cell. When the potential of the source line SL0 is controlled to the second voltage, a cell current smaller than a reference current flows into the memory cell. A sense amplifier 27b outputs data Dout of "0" corresponding to the memory cell in a writing state, i.e., "data 0". <P>COPYRIGHT: (C)2012,JPO&INPIT</p> |
