发明名称 半導体集積回路およびその動作方法
摘要 <p>The present invention is provided to shorten the period of DC offset cancellation operation. One of terminals of two calibration resistors is connected to the differential output terminals of an active low pass filter having a filter process and an amplification function, and two input terminals of a voltage comparator and two terminals of a switch are connected to the other terminal of the two calibration resistors. In a calculation period of calculating digital control signals for reducing DC offset voltage, the voltage comparator detects calibration voltage depending on a voltage drop of one of the calibration resistors caused by analog current of a digital-to-analog converter. In a calibration period of reducing the DC offset voltage, the calibration analog current of the digital-to-analog converter responding to the digital control signal is passed to the input side of the filter via the switch.</p>
申请公布号 JP5611070(B2) 申请公布日期 2014.10.22
申请号 JP20110016387 申请日期 2011.01.28
申请人 发明人
分类号 H03H11/04;H03F3/34;H04B1/16;H04B1/30 主分类号 H03H11/04
代理机构 代理人
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