发明名称 アナログデジタル変換器および信号処理システム
摘要 <p>Disclosed herein is an analog to digital converter including an analog to digital conversion stage of at least one stage adapted to produce digital data of a value corresponding to a relationship to two analog signals inputted thereto and output two analog residual signals. The analog to digital conversion stage includes a signal production section, a comparison section, a first outputting section, a second outputting section, and a changeover section. The comparison section outputs first digital data when a first comparison result that the voltage value of the first analog signal is lower than the voltage value of the second analog signal is obtained whereas the comparison section outputs second digital data when a second comparison result that the voltage value of the first analog signal is higher than the voltage value of the second analog signal is obtained.</p>
申请公布号 JP5609522(B2) 申请公布日期 2014.10.22
申请号 JP20100232877 申请日期 2010.10.15
申请人 发明人
分类号 H03M1/44 主分类号 H03M1/44
代理机构 代理人
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