| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an architecture for self-recovery processor. <P>SOLUTION: A self-recovery system includes a self-recovery processor and an error reduction system. The self-recovery processor includes a code block associated with a partial operation of digital logic. Also the self-recovery processor includes a dynamic signature analysis circuit. The processor executes the code block. The dynamic signature analysis circuit creates a dynamic signature representing a partial operation of the digital logic associated with the code block. The error reduction system receives the dynamic signature from the dynamic signature analysis circuit. The error reduction system compares the dynamic signature with a static signature to determine whether the signatures coincide with each other. If the signatures do not coincide with each other, the digital logic associated with the code block includes an error. The error reduction system retries to execute the code block. The error reduction system stores log information recording the above-described events. <P>COPYRIGHT: (C)2012,JPO&INPIT</p> |
