Power-on-reset circuitry

摘要

Power-on-reset circuitry (22) is provided for integrated circuits such as programmable logic device integrated circuits. The power-on-reset circuitry uses comparator-based trip point voltage detectors (32) to monitor multiple power supply voltages (V PS1 ... V PSn ). The trip point detectors may use circuitry to produce trip point voltages from a bandgap reference voltage (V ref ). Controller logic (38) processes signals from the trip point detectors to produce a corresponding power-on-reset signal (24, POR). The power-on-reset circuitry is sensitive to the power-up sequence used by the power supply signals wherein when the power supply voltages are powered up in a first sequence the power-on-reset signal is deasserted, and when the power supply voltages are powered up in a second sequence that is different than the first sequence the power-on-reset signal remains asserted. The power-on-reset circuitry may contain a noise filter that suppresses noise from power supply voltage spikes. Normal operation of the power-on-reset circuitry may be blocked during testing. The power-on-reset circuitry may be disabled when the bandgap reference voltage has not reached a desired level. Brownout detection blocking circuitry may be provided to prevent the output from one of the trip point detectors from influencing the power-on-reset circuitry.