| 摘要 |
A memory system 100 includes memory controller 110 having error handling logic 112 to compute parity of address signal bits and command signal bits of a command to be sent to RAM memory module 120 and being configured to provide a parity bit signal 140 based on said computed parity when sending the command to memory module 120. Memory module 120 has mode register 122 and error handling logic 124 adapted to detect if the received command has any command/address (C/A) parity error or any cyclic redundancy check (CRC) error. On detection of a parity error, the memory module ignores the received command, stores the command bits and addresses bits of the command in the mode register, and asserts an error indication signal, e.g. a continuous indication signal, to the memory controller. When a CRC error in the command is detected, memory module asserts an indication signal, e.g. for a number of pulses, to the memory controller. Memory controller is further configured to determine from said indication signal whether a parity or a CRC error is present in the command and to perform a recovery mechanism to recover from the parity or CRC error. |
