发明名称 チップ上にネットワークを有するメモリ・デバイスの方法、装置、及びシステム
摘要 <p>Apparatus, method and systems are provided such as those that can include a processor module, an interface device disposed above or below the processor module, the interface device including a plurality of routing elements, at least one memory device disposed above or below the interface device and including a plurality of memory arrays, the plurality of memory arrays coupled to the interface device using a plurality of interconnects provided in vias provided in at least one of the memory device and the interface device. In addition, the interface device communicatively can couple the plurality of memory arrays to the processor module using the plurality of routing elements and the interconnects.</p>
申请公布号 JP5610293(B2) 申请公布日期 2014.10.22
申请号 JP20100546799 申请日期 2009.02.18
申请人 发明人
分类号 G06F13/16;H01L25/065;H01L25/07;H01L25/18 主分类号 G06F13/16
代理机构 代理人
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