发明名称 遅延回路
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a delay circuit capable of reducing a jitter at the time of changing the delay time. <P>SOLUTION: A delay circuit has: first delay elements (131 and 132) connected between a first node and a second node, and that delays a signal at the first node and outputs the delayed signal to the second node; second delay elements (133 and 134) connected between the second node and a third node, and that delays a signal at the second node and outputs the delayed signal to the third node; a phase interpolation circuit (151) that outputs a signal having a phase between the phase of the signal at the first node and that at the second node by weighting the signal at the first node and that at the second node respectively and adding them, or outputs a signal having a phase between the phase of the signal at the second node and that at the third node by weighting the signal at the second node and that at the third node respectively and adding them, depending on a control signal. <P>COPYRIGHT: (C)2012,JPO&INPIT</p>
申请公布号 JP5609287(B2) 申请公布日期 2014.10.22
申请号 JP20100132971 申请日期 2010.06.10
申请人 发明人
分类号 H03K5/14;H03K5/00 主分类号 H03K5/14
代理机构 代理人
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