Memory control device and cache memory controlling method

摘要

A memory control device for controlling an access from a processing unit to a cache memory, the memory control device includes: an address estimation circuit for receiving a first read address of the cache memory from the processing unit and estimating a second read address on the basis of the first read address; an access start detection circuit for detecting an access start of accessing cache memory at the first read address and outputting an access start signal; a data control circuit for receiving read data from the cache memory and for outputting the read data to the processing unit; and a clock control circuit for controlling a read clock to be output to the processing unit in response to the access start signal, the processing unit receiving the read data from the data control circuit with the read clock.

主权项

1. A memory control device for controlling access a cache memory by a processing unit, the memory control device comprising:
an address estimation circuit configured to receive a first read address of the cache memory from the processing unit and estimate a second read address based on the first read address; an access start detection circuit configured to detect an access start of accessing the cache memory at the first read address and output an access start signal; a data control circuit configured to receive read data associated with the first read address from the cache memory and output the read data to the processing unit; and a clock control circuit configured to control a read clock to be output to the processing unit in response to the access start signal, wherein: the processing unit is configured to receive the read data associated with the first read address, based on the read clock from the clock control circuit; and the read data associated with the first read address is one cycle delayed by the data control circuit.