Thin film transistor array panel and method of manufacturing the same

摘要

A TFT array panel and a manufacturing method thereof.;The TFT array panel includes an insulation substrate, a plurality of gate lines, a plurality of first dummy wiring lines, a gate insulating layer, and a plurality of data lines. The insulation substrate has a display area for displaying an image and a peripheral area outside the display area. The plurality of gate lines are formed in the display area and in a portion of the peripheral area. The plurality of first dummy wiring lines are insulated from the gate lines and formed in the peripheral area. The gate insulating later is formed on the gate lines and the first dummy wiring lines, and has at least one contact hole exposing at least lateral end portions of the first dummy wiring lines. The plurality of gate lines are formed on the gate insulating layer, define a plurality of pixel areas that form the display area by being insulated from the plurality of gate lines and crossing the plurality of gate lines, and are connected with the at least lateral end portions of the first dummy wiring lines through the at least one contact hole. With this configuration, data voltages can be efficiently applied to respective pixel electrodes of the display area even though the data line, particularly the data fan-out unit, in the peripheral area is disconnected.

主权项

1. A method for manufacturing a thin film transistor (TFT) array panel, the method comprising: forming an insulation substrate having a display area for displaying an image and a peripheral area outside the display area;
forming a plurality of gate lines in the display area and in a part of the peripheral area and a first dummy wiring line insulated from the gate lines in the peripheral area; forming a gate insulating layer on the gate line and on the first dummy wiring line; forming at least one contact hole that exposes at least ends of the first dummy wiring line by patterning the gate insulating layer; and forming a plurality of data lines directly connected with the ends of the first dummy wiring line through the at least one contact hole on the gate insulating layer.