Small, adaptable, real-time, scalable image processing chip

摘要

An imaging solution that uses a small, adaptable, real-time, scalable, image-processing (SMARTS IP) chip configured to function like any one of a wide range of specialized FPA imaging devices, and a method for configuring and implementing same is provided. Configuration for a wide range of applications and implementations, including ones with or without IDCA assemblies or other types of dewar/cooler structures, is disclosed. A wide range of output data formats, including all SDI-compatible image data formats, may be accomplished. Frame stacking and variable effective resolution and charge well depth levels may be accomplished in output image data based on on-chip image processing techniques. On-chip image processing algorithms may include XR™, DRC, NUC, and other similar or related techniques. Image data output compression through on-chip processing is also disclosed.

主权项

1. A method of making an image generation system comprising:
connecting a programmable image processing chip to a read-out integrated circuit of a 1296×1040 12 μm pixel pitch infra-red focal plane array (FPA) device; programming a desired image processing algorithm into said programmable image processing chip; configuring the programmable image processing chip to read and output image data from the FPA device as though the FPA device was one of a: 1280×1024 FPA device comprising a 12 μm pixel pitch, a 640×512 FPA device comprising up to a 24 μm pixel pitch, or a 320×256 FPA device comprising up to a 48 μm pixel pitch; and interfacing said programmable image processing chip with image output and post-capture processing hardware.