Standard cells having transistors annotated for gate-length biasing

摘要

A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

主权项

1. A standard cell library stored on a non-transitory computer readable storage, the standard cell library used by a processor to produce a layout for fabricating at least one aspect of a finished semiconductor device, comprising:
the standard cell library containing cells wherein at least one transistor in at least one cell is identified by an annotation layer, and the annotation layer itself also identifies a gate length biasing to be applied to the at least one transistor of the at least one cell when the processor produces the layout, wherein the gate length biasing is an amount of change to a gate length of the at least one transistor, the amount of change is associated with shapes in the annotation layer and the amount of change identified using the annotation layer is a design-specific directive that communicates the gate length biasing.