Multiport memory with matching address and data line control

摘要

In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic. A second data line pair is coupled to the first bit line pair via second switching logic and to the second bit line pair via third switching logic. If a row address match but not a column address match exists between a first and second access address, the second switching logic selectively connects the second data line pair with the first bit line pair based on a first decoded signal generated from the column address of the second access address and the third switching logic decouples the second data line pair from the second bit line pair.

主权项

1. A multiple port static random access memory (SRAM) having a first port and a second port, comprising:
a first word line and a second word line of a plurality of word lines; a first bit line pair, a second bit line pair, a third bit line pair, and a fourth bit line pair of a plurality of bit line pairs; an array of bit cells coupled to the plurality of word lines and the plurality of bit line pairs, wherein the array of bit cells comprises:
a first bit cell having a first storage latch, and coupled to the first word line and the first bit line pair to access the first storage latch, and coupled to the second word line and the second bit line pair to access the first storage latch; a first read/write data line pair of a first plurality of read/write data line pairs for accessing the array of bit cells, and a second read/write data line pair of a second plurality of read/write data line pairs for accessing the array of bit cells, wherein:
the first read/write data line pair is coupled to the first bit line pair via first switching logic; andthe second read/write data line pair is coupled to the first bit line pair via second switching logic and coupled to the second bit line pair via third switching logic; a row match detector which provides a row match indicator based on whether a row address of a first access address matches a row address of a second access address; and a column match detector which provides a column match indicator based on whether a column address of the first access address matches a column address of the second access address, wherein in response to the row match indicator indicating a match and the column match indicator not indicating a match, the second switching logic selectively connects the second read/write data line pair with the first bit line pair based on a first decoded signal generated from the column address of the second access address and the third switching logic decouples the second read/write data line pair from the second bit line pair.