发明名称 Ta—TaN selective removal process for integrated device fabrication
摘要 Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.
申请公布号 US8865597(B2) 申请公布日期 2014.10.21
申请号 US201313772511 申请日期 2013.02.21
申请人 International Business Machines Corporation 发明人 Cotte John M.;Hoivik Nils;Jahnes Christopher V.;Wisnieff Robert L.
分类号 H01L21/302;C23F1/00;H01L23/00;H01L21/768;H01L21/306;H01L21/3213;H01L23/522;H01L23/532 主分类号 H01L21/302
代理机构 Scully, Scott, Murphy & Presser PC 代理人 Scully, Scott, Murphy & Presser PC ;Percello, Esq. Louis J.
主权项 1. A method of exposing a semiconductor structure to multiple gases using a dual chamber, dual pressure device including first and second chambers and a connecting line connecting the first and second chambers together, the semiconductor structure including a layer of a dielectric material, and a TaN—Ta liner on the dielectric layer, and a copper layer on the TaN—Ta liner, and wherein a chemical mechanical polishing (CMP) process is used to polish the copper layer and said CMP process exposes portions of the TaN—Ta liner, the method comprising: placing the semiconductor structure in the second chamber of the dual chamber, dual pressure device; establishing a first pressure in the first chamber and a second pressure in the second chamber, said first pressure being greater than said second pressure; exposing the first chamber to a source of a first gas; using a first valve in the connecting line to expose the semiconductor structure in the second chamber to the first gas from the first chamber after said CMP process, and for using said first gas to selectively etch at least a portion of the TaN—Ta liner completely to the dielectric layer while preserving all the dielectric layer; using a sub-system connected to the connecting line to conduct a plurality of additional gases into the second chamber via the connecting line.
地址 Armonk NY US