On-the-fly permutation of vector elements for executing successive elemental instructions

摘要

A device system and method for processing program instructions, for example, to execute intra vector operations. A fetch unit may receive a program instruction defining different operations on data elements stored at the same vector memory address. A processor may include different types of execution units each executing a different one of a predetermined plurality of elemental instructions. Each program instruction may be a combination of one or more of the elemental instructions. The processor may receive a vector of data elements stored non-consecutively at the same vector memory address to be processed by a same one of the elemental instructions and a vector of configuration values independently associated with executing the same elemental instruction on the non-consecutive data elements. At least two configuration values may be different to implement different operations by executing the same elemental instruction using the different configuration values on the vector of non-consecutive data elements.

主权项

1. A method comprising:
at a first stage:
loading, from a data memory into a configuration vector memory within a processor configuration values, pointers to non-consecutive elements of data elements, stored at a source vector memory within the processor to be used for executing a program instruction;wherein the program instruction is a combination of two or more of predetermined elemental instructions, each elemental instruction executable at a different type of execution unit within the processor; and at a second stage:
executing the elemental instructions of the program instruction in successive operations, wherein executing a first elemental instruction comprises:
using a first portion of the configuration values stored at the configuration vector memory to permute on-the-fly data elements in the source vector memory such that non-consecutive data elements are input to a first-type execution unit;executing the first elemental instruction in the first-type execution unit according to the first portion of the configuration values; andoutputting the result of the first-type execution unit to a first-result vector memory, which serves as a source vector register for a second-type execution unit which executes a second successive elemental instruction;executing the second elemental instruction in the second-type execution unit according to a second portion of the configuration values stored at a second configuration vector memory and values stored at the first-result vector memory; and outputting the result of the second-type execution unit to a second-result vector memory, wherein each type of execution unit comprises parallel execution units to execute the corresponding elemental instruction in parallel.