发明名称 Semiconductor package and fabrication method thereof
摘要 A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.
申请公布号 US8865523(B2) 申请公布日期 2014.10.21
申请号 US201313833341 申请日期 2013.03.15
申请人 Alpha & Omega Semiconductor, Inc. 发明人 Ho Yueh-Se;Xue Yan Xun;Lu Jun;Shi Lei;Zhao Liang;Huang Ping
分类号 H01L23/495;H01L21/78 主分类号 H01L23/495
代理机构 CH Emily LLC 代理人 Tsao Chein-Hwa;CH Emily LLC
主权项 1. A fabrication method of a semiconductor device is characterized by comprising the following steps: Step 1, forming a plurality of semiconductor chips on a semiconductor wafer, wherein each semiconductor chip includes a first top terminal and a second top terminal arranged at a top surface of the semiconductor wafer and a bottom terminal arranged at a bottom portion of the semiconductor wafer; Step 2, forming a conductive contact body on each top terminal at the top surface of the semiconductor wafer corresponding to each top terminal respectively; Step 3, molding the top surface of the wafer to form a first plastic package body covering top surfaces of each semiconductor chip and at least sidewalls of each contact body; Step 4, grinding a bottom surface of the molded semiconductor wafer to a predetermined wafer thickness and cutting the ground semiconductor wafer to separate individual molded chips; Step 5, providing a conductive lead frame, wherein the lead frame comprises a die paddle surrounded by a periphery with opposite first side and third side and opposite second side and fourth side and a contact part formed at each of the first side and the third side of the lead frame connecting to the die paddle, wherein a top surface of the contact part is higher than a top surface of the die paddle; Step 6, mounting the bottom surface of a molded semiconductor chip onto the top surface of the die paddle of the lead frame such that the bottom terminal of the semiconductor chip is electrically connected to the die pad; Step 7, molding the lead frame connected with the chip with a second plastic package body such that top surfaces of the contact body of each top terminal on the semiconductor chip and the contact part of the lead frame are respectively exposed outside a top surface of the second plastic package body for external electric connection, and a bottom surface of the die paddle on the lead frame is exposed outside of a bottom surface of the second plastic package body for heat dissipation; Step 8, forming a patterned metal plating layer as external connection pads of the corresponding terminals on a top surface of the overall packaging structure including the exposed surfaces of each contact body and the contact part, wherein a first pad in electric connection with the contact part respectively extends to edges of the first side and the third side, a second pad in electric connection with the first top terminal extends to an edge of the second side but terminates far away from the edges of the first side and the third side, and a third pad in electric connection with the second top terminal extends to an edge of the fourth side but terminates far away from the edges of the first side and the third side.
地址 Sunnyvale CA US