Dual flip-flop circuit

摘要

A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.

主权项

1. A dual flip-flop circuit, comprising:
a first flip-flop sub-circuit comprising:
a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels;a clock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal; anda first selection sub-circuit that is coupled to the first storage sub-circuit and configured to receive first complementary scan input signals representing a first scan input signal, and based on a first scan enable signal and an inverted first scan enable signal, output either the first scan input signal or a first data signal as the first selected input signal; and a second flip-flop sub-circuit that is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal, the second flip-flop sub-circuit comprising a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions between two different logic levels.