Data input circuit

摘要

A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal.

主权项

1. A data input circuit comprising:
a data alignment unit configured to align internal data in synchronization with first and second internal strobe signals to generate rising data and falling data; a data strobe signal detection circuit configured to detect a last falling edge of a data strobe signal and generate a write latch signal; and a data latch unit configured to latch the rising data and the falling data in response to the write latch signal and output latched data.