FIFO apparatus for the boundary of clock trees and method thereof

摘要

A FIFO apparatus uses a first clock signal in a first clock domain to receive an input signal and uses a second clock signal in a second clock domain to output an output signal. An example apparatus includes: at least three write registers belonging to the first clock domain for receiving the input signal. Each of the write registers has a first output. A first controller belonging to the first clock domain enables the registers, in accordance with an order, to generate an initial signal. A multiplexer receives the first outputs. A second controller belonging to the second clock domain, receives the initial signal through an asynchronous interface and controls the multiplexer to output the first outputs in accordance with the order to be the output signal, wherein the second clock domain is a clock tree generated based on the first clock domain.

主权项

1. A first in and first out (FIFO) apparatus, utilizing a first clock signal of a first clock domain to receive an input signal, and utilizing a second clock signal of a second clock domain to output an output signal, wherein the apparatus comprises:
at least three write registers, in the first clock domain, for receiving the input signal, wherein each write register has a first input; a first controller, in the first clock domain, for enabling the at least three write registers in accordance with a sequence and generating an initial signal; a multiplexer for receiving the first outputs; and a second controller, in the second clock domain, for receiving the initial signal through an asynchronous interface and controlling the multiplexer to output the first outputs as the output signal in accordance with the sequence according to the initial signal; wherein the second clock domain is based on a clock tree generated according to the first clock domain.