Method and apparatus for performing multiplication in a processor

摘要

A method and apparatus are described for performing multiplication in a processor to generate a product. In one embodiment, a 64-bit multiplier and a 64-bit multiplicand may be multiplied together over four cycles by merging different partial product (PP) subsets, generated by a Booth encoder and a PP generator, with feedback sum and carry results. The logic inputs of a plurality of multiplexers may be selected on a cyclical basis to efficiently compress (i.e., merge) each PP subset with feedback sum and carry results. A pair of preliminary sum results stored during one cycle may be outputted during a subsequent cycle and processed by a logic gate (e.g., an XOR gate) to generate a feedback sum result that is merged with a feedback carry result and a PP subset. Final sum and carry results may be added to generate the product of the multiplier and the multiplicand.

主权项

1. A method of a processor performing multiplication of a multiplier and a multiplicand to generate a product, the method comprising:
a) during a first cycle of the processor,
generating a first subset of a plurality of partial products (PPs) based on the multiplier and the multiplicand; andstoring in respective storage devices a pair of preliminary sum results and a carry result obtained by merging the first subset of PPs; b) during another cycle of the processor:
generating an additional subset of the PPs based on the multiplier and the multiplicand;outputting the pair of preliminary sum results and a feedback carry result from the respective storage devices; andprocessing the pair of preliminary sum results to generate a feedback sum result; c) if all of the PPs have not been generated:
storing in the respective storage devices a pair of preliminary sum results and a carry result obtained by merging the feedback sum result, the feedback carry result and the additional subset of PPs; andrepeating step b); and d) if all of the PPs have been generated:
storing in respective storage devices a final sum result and a final carry result obtained by merging the feedback sum result, the feedback carry result and the additional subset of PPs; andadding the final sum result and the final carry result to generate the product.